VHDL Editor
The built-in editor performs color highlighting of VHDL
source code to facilitate reading, and automatic identifier
completion to reduce typing.
State Machine Editor
The most intuitive way to design a state machine is with a
state machine diagram. VHDL Studio™ includes a graphical
state machine diagram editor for intuitive state machine
entry that automatically and transparently generates a
VHDL implementation.
On-the-fly Error Detection
Using incremental analysis, VHDL Studio™ can instantly
detect syntax errors as you type and eliminate the tedious compile, locate error, and edit cycle.
Auto-prompting
Auto prompts provide you quick
information about previously defined
subprogram signatures, and signal/
variable types without leaving your
current editing position to locate the
definition in another location or even
in another file. Auto prompts are always up-to-date due to VHDL Studio’s incremental analysis
engine.
Instance/Component Creators
Component and instance wizards make component declaration
and instantiation a snap. Just select any entity from your
project and the component creator will insert a matching
component declaration in your design. The instance creator
provides a simple graphical interface for assigning local signals to the ports of the instantiated entity for fast, errorfree component
instantiation.
Graphical Testbench Designer
The testbench designer provides a graphical waveform editor for
simple and intuitive testbench design. In interactive mode, the
simulator updates output waveforms as you edit the inputs.
Timing checks and data checkpoints are also easily added to
the waveform diagram. You can run the testbench within VHDL
studio for a graphical display of timing and data violations or run
the automatically-generated VHDL testbench yourself.
| Simulation |
Native VHDL’93 Compiler VHDL Studio™ includes a new version of the Green Mountain
VHDL Compiler for fast, direct-compile simulation.
Waveform Display Graphical waveform display makes simulation results easy to
browse and understand.
| Source-Level Debugging |
Source-level debugging provides statementbystatement
execution for detailed
debugging. Source-level debugging includes
breakpoints to quickly simulate to the point
of interest for detailed, statement-bystatement
debugging.
Tcl/Tk Scripting The simulator provides Tcl/Tk script support
to enable unlimited customization and
automation.
VITAL Optimization The new version of the Green Mountain VHDL Compiler in VHDL
Studio™ includes VITAL specific optimizations and built-in
VITAL libraries delivering performance up to 7 times faster than
the previous version.
SDF Backannotation Post-route simulation with timing information is provided through
standard SDF backannotation.
| Project Management |
Hierarchy Browser The hierarchy browser provides a complete structural view of
your design’s units, blocks, instances and processes, as well
as type, signal, variable, and
subprogram information. Double
clicking on any item in the browser
instantly brings you to the file and
line number where the item is
defined. Thanks to VHDL Studio’s
incremental analysis, the browser
is always up-to-date with changes
made in the editor.
Hypertext Navigation In VHDL Studio™ your VHDL is
more than plain text, its hypertext! If you forget the type of that signal, or the arguments to that
function, simply right click on its name to instantly jump to its
definition.
Navigation History Even with all the advanced design navigation features of VHDL
Studio™. you’ll never get lost with the “back” button, which will
quickly return you to your previous location in the design.
| System Requirements |
Windows
- Pentium PC/64MB of RAM
- Microsoft Windows 98, Me, NT 4.0, or 2000
- 20MB of hard-disk space (installation only).
- CD-ROM
Linux
- Pentium PC/64MB of RAM
- Linux 2.0 or greater
- 20MB of hard-disk space (installation only)
- CD-ROM
Solaris
- Sparc V8 or better/64MB of RAM
- Solaris 2.7 or 2.8
- 20MB of hard-disk space (installation only)
- CD-ROM
Components
- On-line VHDL Tutorial
- On-line VHDL Reference Manual
- On-line User’s Guide
- Project Wizard
- Project Manager
- Design Browser
- VHDL Editor
- Incremental Analysis
- State Machine Editor
- Instance Wizard
- Test Bench Generator
- VHDL’93 Simulation
- Source-Level Debugger
- Waveform Viewer
- VITAL/SDF Simulation
- Tcl/Tk Scripting
Learn VHDL the Direct way with our low-cost, interactive
VHDL simulator. DirectVHDL is built around a VHDL
interpreter that allows you to edit and simulate your
VHDL design without complicated setup or compilation
procedures. DirectVHDL simply loads and simulates in
one step.
DirectVHDL includes the following:
- VHDL Workspace
An easy-to-use manager that serves as a starting point to
launch the VHDL editor and simulator.
- VHDL Editor
An advanced editor providing syntax coloring and syntaxerror
detection. Perfect for beginners, this editor highlights
syntax errors as you type!
- VHDL Simulator
Allows you to simulate and debug your design with a
graphical waveform viewer. - VHDL Tutorial
Provides an easy introduction to the VHDL language.
| Requirements |
- Windows
Windows 95,98,Me,NT 4.0, or 2000, 15 MB hard disk
space, 64 MB RAM.
- Mac OS X
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