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FPGA Trainer
FPGA DIGITAL LOGIC LAB-II
FEATURES
It has an
INCODE Software
to enable user to
Download Program
Upload Program
Run Program
Upload Data from RAM into a file
Download Data from a file onto the RAM
Register Setting
Download Configuration
Download FPGA data
Download FPGA Data from a file
Upload FPGA Data
Upload FPGA Data to file
Diagnostic Mode
Settings
User can develop the circuit/schematic using Xilinx standard Foundation Series Software.
It has a serial link which enables user to communicate with PC at a standard baud rate.
It has level microcontroller 8051 family processor to enable it to upload and download program to/from FPGA.
Field Programmable Gate Array Trainer commonly known as FPGA Trainer uses industrial standard Xilinx FPGA 3142.
All the pin outs of FPGA are available on the board. This helps in man - machine interface.
System has 64K byte of EPROM & 32K byte of RAM.
It has I/O counter interface to enable it to connect to various demo modules. This helps in man to machine interface.
SPECIFICATIONS
Linear unit:
1. 1 set 8 bit D/A converter
2. 1 set 8 bit A/D converter
Output unit:
1. 8 x 8 of matrix (LED) display
2. 2 x 3 seven segment display
3. 16 x 1 LCD display
4. 1 set buzzer output
5. 1 x 4 and 1 x 8 bar code output
6. 12 x 1 LED display to perform traffic light experiment
Logic input switch:
1. 8 x 1 logic input original press point with light
2. 8 x 2 logic input Dip switch
3. 4 impulse press button generator (2 positive pulse 2 negative pulse)
Supported chip: Xilinx 3142 on board experiments.
Signal generation unit:
1. Programmable frequency generator
2. Standard frequency 1/10/100/1K/10K/100IK/1M/ 10MHz
Case Studies:
1. FIFO Unit
2. Ping Pong Unit
3. Stack Machine
4. Hardware Sorter
MPU unit:
8051 operations
Library Components:
In order to facilitate a smooth operation for the user who, wish directly go ahead with their designs.
1. Bounce Eliminator
2. PC Interfacing Module (PC Input/Output)
3. PC Interfacing Module (PC RAM)
4. Up-down Counter
5. Sequential Divider
6. First in First out Buffer (FIFO)
7. Hamming Distance Calculator
8. Incrementor
9. Last in First Out Buffer (LIFO)
10. L.C.D. Interface
11. DAC Interface
12. ADC Interface
13. Keyboard Interface
14. 8 x 8 LED Matrix
15. Seven Segment
THEMATIC APPLICATION TEST
8 x 8 LED control test
Counter
Keyboard scan
LCD display control test
A/D, D/A converter test
Easy CPU design
Matching 8051 thematic test
Stepper motor driver design
APPLICATION PROGRAM RANGE
VLSI design program
Micro processor principle program
Digital system design circuit program
Digital circuit design program
Fundamental logic program
Thematic preparation
8051 single chip program
CPLD/FPGA chip design program
ELECTRICAL SPECIFICATION
220V, 50HZ AC INPUT
SERIAL PORT DOWNLOAD INTERFACE
FPGA DIGITAL LOGIC LAB - II
Uses industrial standard Xilinx FPGA 4010.
VPL Infotech & Consultants 301, Savitri Sadan II, 15 Community Centre, Preet Vihar Delhi, India Tel: +91-11-22542234,22546754
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